Enterprise storage leader HGST is previewing a new architecture for solid-state drives (SSDs) that enables applications to provide faster insights to the data-intensive questions of tomorrow. The demonstration shows unprecedented SSD performance levels that are achieved by utilizing a combination of HGST’s new, latency-optimized interface protocols with next-generation non-volatile memory components.
The SSD demonstration utilizes a PCIe interface and delivers three million random read IOs per second of 512 Bytes each when operating in a queued environment and a random read access latency of 1.5 microseconds (us) in non-queued settings, delivering results that cannot be achieved with existing SSD architectures and NAND Flash memories. This performance is orders of magnitude faster than existing Flash based SSDs, resulting in a new class of block storage devices.
The memory used in this SSD consists of Phase Change Memory (PCM) components with a capacity of 1Gb. PCM is one of several new classes of high-density, non-volatile memories that exhibit dramatically faster read access times when compared to NAND Flash memory.
In order to fully expose the capabilities of these new memory technologies to the server system and its software applications, HGST has also developed a low-latency interface architecture that is fully optimized for performance and is agnostic to the specific underlying memory technology. HGST used its controller expertise to integrate the 45 nm 1Gb PCM chips to build a prototype full height, full length PCIe Gen 2×4 SSD card.
To achieve latencies close to 1us, HGST devised, in conjunction with researchers at the University of California, San Diego, a new communication protocol. This new interface protocol was introduced earlier this year at the 2014 Use nix conference on File and Storage Technologies (FAST).
The most dramatic advantage these emerging NVMs have over NAND flash is that their read latency is shorter by more than two orders of magnitude. In order to harness this intrinsic advantage, new controller and interface technologies are needed. Current state-of-the-art NVMe protocol is not a problem in the context of NAND Flash but will be inadequate for these emerging NVM technologies that will introduce a new class of storage into the data center ecosystem.